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ibis4-6600 cyii4sm6600ab 6.6 mp cmos image sensor cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-02366 rev. *f revised september 18, 2009 features 2210 (h) x 3002 (v) active pixels 3.5 m x 3.5 m square pixels 1 inch optical format monochrome or color digital output frame rate: ? 5 fps (2210 x 3002) ? 89 fps (640 x 480) high dynamic range modes: double slope, non destructive read out (ndr) electronic rolling shutter master clock: 40 mps/40 mhz limited supplies: 2.5v and 3.3v -30c to +65c operational temperature range 68-pin lcc package power dissipation: 0.19w applications machine vision biometry document scanning description the ibis4-6600 is a solid-state cmos image sensor that integrates complete analog image acquisition, and a digitizer and digital signal processing system on a single chip. this image sensor has a resolution of 6.6 mpixel with 2210 x 3002 active pixels. the image size is fully programmable for user-defined windows. the pixels are on a 3. 5 m pitch. this sensor is available in a monochrome version or bayer (rgb) patterned color filter array. the user programmable row and column start and stop positions enable windowing down to 2x1 pixel window for digital zoom. sub sampling reduces resolution while maintaining the constant field of view. the analog video output of the pixel array is processed by an on-chip analog signal pipeline. double sampling (ds) eliminates the fixed pattern noise. the programmable gain and offset amplifier maps the signal swing to the adc input range. a 10-bit adc converts the analog data to a 10-bit digital word stream. the sensor uses a three-wire serial-parallel (spi) interface. it operates with a single 2.5v power supply and requires only one master clock for operation up to 40 mhz. it is housed in a 68-pin ceramic lcc package. this data sheet enables you to develop a camera system, based on the described timing and interfacing given in the following sections. figure 1. ibis4-6600 image sensor [+] feedback
ibis4-6600 cyii4sm6600ab document number: 001-02366 rev. *f page 2 of 34 ordering information specifications marketing part number description package CYII4SM6600AB-QDC mono with glass 68-pin lcc cyii4sm6600ab-qwc mono without glass cyii4sc6600ab-qdc color with glass cyii4se6600ab-qdc color micro lens with glass cyii4se6600ab-qfch color micro lens with ir coating, high grade cyii4sm6600-eval mono demo kit demo kit cyii4sc6600-eval color demo kit general specifications parameter specification remarks pixel architecture 3t-pixel pixel size 3.5 m x 3.5 m the resolution and pi xel size results in a 7.74 mm x 10.51 mm optical active area. resolution 2210 x 3002 pixel rate 40 mhz using a 40 mhz system clock and 1 or 2 parallel outputs shutter type electronic rolling shutter full frame rate 5 frames/second increases with roi read out and/or subsampling electro optical specifications parameter specification remarks fpn (local) <0.20% rms% of saturation signal prnu (local) <1.5% rms of signal level conversion gain conversion gain at output (measured) output signal amplitude 0.6v at nominal conditions saturation charge 21.500 e- sensitivity (peak) 411 v.m 2 /w.s 4.83 v/lux.s at 650 nm (85 lux = 1 w/m 2 ) sensitivity (visible) 328 v.m 2 /w.s 2.01 v/lux.s 400-700 nm (163 lux = 1 w/m 2 ) peak qe * ff peak spectral response 25% 0.13 a/w average qe*ff = 22% (visible range) average sr*ff = 0.1 a/w (visible range) see the section spectral response curve on page 3. fill factor 35% light sensitive part of pixel (measured) dark current 3.37 mv/s 78 e-/s typical value of average dark current of the whole pixel array (at 21c) dark signal non uniformity 8.28 mv/s 191 e-/s dark current rms value (at 21c) temporal noise 24 rms e- measured at digital output (in the dark) s/n ratio 895:1 (59 db) measured at digital output (in the dark) spectral sensitivity range 400 - 1000 nm optical cross talk 15% 4% to the first neighboring pixel to the second neighboring pixel power dissipation 190 mw typical (including adcs) [+] feedback
ibis4-6600 cyii4sm6600ab document number: 001-02366 rev. *f page 3 of 34 spectral response curve figure 2. spectral response curve figure 2 shows the characteristics of the spectral response. the curve is measured directly on the pixels. it includes the effects of nonsensitive areas in the pixel, for example, interconnection l ines. the sensor is light sensitive between 400 and 1000 nm. the peak qe * ff is 25% approximately 650 nm. in view of a fill factor of 35%, the qe is close to 70% between 500 and 700 nm. 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 400 500 600 700 800 900 1000 wavelenght [nm] spectral response [a/w] qe 10% qe 20% qe 30% [+] feedback
ibis4-6600 cyii4sm6600ab document number: 001-02366 rev. *f page 4 of 34 electro voltaic response curve figure 3. electro voltaic response curve figure 3 shows the pixel response curve in linear response mode. this curve is the relation between the electrons detected in the pixel and the output signal. the resulting voltage-electron cu rve is independent of any parameters, for example, integration ti me. the voltage to electrons conversion gain is 43 v/electron. table 1. features and general specifications feature specification/description electronic shutter type rolling shutter integration time control 60 s - 1/frame period windowing (roi) randomly programmable roi read out sub sampling modes several sub sample modes can be programmed (refer table 7 on page 12) extended dynamic range dual slope (up to 90 db opti cal dynamic range) and nondestructive read out mode analog output the output rate of 40 mpixels/s can be achieved with two analog outputs, each working at 20 mpixel/s digital output two on-chip 10-bit adcs at 20 msampl es/s are multiplexed to one digital 10-bit output at 40 msamples/s supply voltage v dd nominal 2.5v (some supplies requir e 3.3v for extended dynamic range) logic levels 2.5v interface serial-to parallel interface (spi) package 68-pins lcc 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0 5000 10000 15000 20000 25000 # electrons output swing [v] [+] feedback
ibis4-6600 cyii4sm6600ab document number: 001-02366 rev. *f page 5 of 34 electrical specifications absolute maximum ratings exceeding maximum ratings may shorten the useful life of the devic e. user guidelines are not test ed. stresses beyond those list ed under ta b l e 2 may cause permanent damage to the device. these are stress ratings only and the functional operation of the device at these or any other conditions beyond those indicated in the operat ional sections are not implied. all parameters are characterized for dc conditions after thermal e quilibrium is established. unused inputs must always be tied to an appropriate logic level, for example, v dd or gnd. this device contains circuitry to protect the inputs against dam age caused by high static voltages or electric fields. however, you must take normal precautions to avoid applying voltages higher than the maximum rated voltages to this high impedance circuit. table 2. absolute maximum ratings symbol parameter value unit v dd [1] dc supply voltage ?0.5 to 3.3 v v in dc input voltage ?0.5 to (v dd + 0.5) v v out dc output voltage ?0.5 to (v dd + 0.5) v i io dc current drain per pin; any single input or output 50 ma t l lead temperature (5 seconds soldering) 350 c t st storage temperature ?30 to +85 c h humidity (relative) 85% at 85 c esd esd susceptibility 2000 v recommended operating conditions symbol parameter min typ max unit v dd dc supply voltage 2.5 2.5 3.3 v t a commercial operating temperature ?30 24 +65 c note 1. v dd = v ddd = v dda (v ddd is supply to digital circuit, v dda to analog circuit). dc electrical conditions symbol characteristic condition min max unit v ih input high voltage v dd -0.5 v v il input low voltage ?0.6 0.6 v i in input leakage current v in = v dd or gnd ?10 +10 a v oh output high voltage v dd =min; i oh = ?100 ma v dd -0.5 v v ol output low voltage v dd =min; i oh = 100 ma 0.5 v i dd operating current system clock <= 40 mhz 70 80 ma [+] feedback
ibis4-6600 cyii4sm6600ab document number: 001-02366 rev. *f page 6 of 34 sensor architecture and operation floor plan figure 4. floor plan figure 4 shows the architecture of the designed image sensor. it consists of the pixel array, shift registers for the readout in x and y direction, parallel analog output amplifiers, and column amplifiers that correct for the fixed pattern noise caused by threshold voltage nonuniformities. reading out the pixel array starts by applying a y clock pulse to select a new row, followed by a calibration sequence to calibrate the column amplifiers (row blanking time). depending on external bias resistors and timing, typically this sequence takes about seven seconds every line (baseline). this sequence is necessary to remove the fixed pattern noise of the pixel and of the column amplifiers themselves (by a double sampling technique). pixels can also be read out in a nondestructive manner. two dacs are added to make the offset level of the pixel values adjustable and equal for the two output buses. a third dac is used to connect the buses to a stable voltage during the row blanking period, or reset the buses continuously in case of a nondestructive readout. two 10-bit adcs running at 20 msamples/s convert the analog pixel values. the digital outputs are multiplexed to one digital 10-bit output at 40 msamples/s . note that these blocks are electrically completely isolated fr om the sensor part, except for the multiplexer, for which the settings are uploaded through the shared address and data bus. the x and y shift registers have a programmable starting point. the possibilities of the start ing point are limited because of limitations imposed by subsampling requirements. the start address is uploaded through the serial to parallel interface. most of the signals for the image core shown in figure 4 are generated on-chip by the sequenc er. this sequencer also allows running the sensor in basic modes, not fully autonomous. res et select analog output (2) eos_yl eos_yr tri l tri r dac in adc, 10 bit adc, 10 bit sequencer image c or e sensor spi pixel array 2210 x 3002 (excl. dark + dummy pixels ) addressable x-shift register + sub-sampling addres s able y-s hift regis ter + s ub-s ampling column ampli?ers res et and s elect drivers res et and s elect drivers clk_y sync_yl clk_x sync_x pixel (0,0) dac addres s able y-s hift regis ter + s ub-s ampling clk_y sync_y r dig. logic dig. logic addres s & data bus [+] feedback
ibis4-6600 cyii4sm6600ab document number: 001-02366 rev. *f page 7 of 34 pixel architecture the pixel architecture is the cl assic three-transistor pixel, as shown in figure 5 the pixel is implemented using the high fill factor technique patented by fillfactory (us patent no. 6,225,670 and others). figure 5. 3t pixel architecture fpn and prnu fixed pattern noise correction is done on-chip. raw images taken by the sensor typically feature a residual (local) fpn of 0.35% rms of the saturation voltage. the photo response non uniformity (prnu), caused by the mismatch of photodiode node capacitances, is not corrected on chip. measurements indicate that the typical prnu is about 1.5% rms of the signal level. color filter array the ibis4-6600 can also be processed with a bayer rgb color pattern. pixel (0,0) has a green filter and is situated on a green-red row. green1 and green2 are separately processed color filters and have a different spectral response. green1 pixels are located on a blue-green row, and green2 pixels are located on a green-red row. figure 6. rgb bayer alignment figure 7 shows the response of the c olor filter array as function of the wavelength. figure 7. typical response curve of the rgb filters selec vdd m1 m2 m3 reset output (column) select 0.000 0.020 0.040 0.060 0.080 0.100 0.120 0.140 400 500 600 700 800 900 1000 wavelength [nm] blue green 1 green 2 red mono spectral response [a/w] [+] feedback
ibis4-6600 cyii4sm6600ab document number: 001-02366 rev. *f page 8 of 34 figure 8. relative response graph dark and dummy pixels figure 9 shows a plan of the pixel array. the sensor is designed in po rtrait orientation. a ring of dummy pixels surrounds the active pixels. black pixels are implemented as "optical" black pixels. figure 9. floor plan pixel array 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 400 500 600 700 800 900 1000 wavelength (nm) blue green 1 green 2 red relative response dummy ring of pixels , s urrounding complete pixel array. not read r ing of 2 dummy pixels , illuminated, readable array of active pixels, read 3002x 2210 r ing of dummy pixels , covered with black layer, readable 2222 3014 2210 3002 [+] feedback
ibis4-6600 cyii4sm6600ab document number: 001-02366 rev. *f page 9 of 34 pixel rate the pixel rate for this sensor is high enough to support a frame rate greater than 75 hz for a window size of 640 x 480 pixels (vga format), and 23 pixels over scan in both directions. taking into account a row blanking time of 7.2 s (as baseline, refer the following calculations), this requires a minimum pixel rate of approximately 40 mhz. the final bandwidth of the column amplifiers, output stage, and more is determined by external bias resistors. taking into account a pixel rate of 40 mhz, a full frame rate of a little more than 5 frames/s is obtained. the frame period of the ibis4- 6600 sensor is calculated as: => frame period = (nr. lines * ( rbt + pixel period * nr. pixels)) in this equation: nr. lines: number of lines read out each frame (y) nr. pixels: number of pixels read out each line (x) rbt: row blanking time = 7.2 s (typical) pixel period: 1/40 mhz = 25 ns example: read out time of the full resolution at nominal speed (40 mhz pixel rate): => frame period = (3002 * (7.2 s + 25 ns * 2210)) = 187.5 ms => 5.33 fps. region of interest (roi) read out windowing is easily achieved by uploading the starting point of the x and y-shift registers in the sensor registers (refer table 10 on page 17). this downloaded starting point initiates the shift register in the x and y-direct ion, triggered by the y_start (initiates the y-shift register) and the y_clk (initiates the x-shift register) pulse. the minimum step size for the x-address is 24 (only even start addresses can be chosen) and 1 for the y-address (every line can be addressed). the frame rate increases in an almost linear manner when fewer pixels are read out. table 3 lists the achievable frame rates with roi read out. output amplifier the output amplifier subtracts t he reset and signal voltages from each other to cancel fpn as much as possible (shown in figure 10 ). the dac that is used fo r offset adjustment consists of two dacs. one dac is used for the main offset (dac_raw). the other enables fine tuning to compensate the offset difference between the signal paths arriving at the two amplifiers a1 and a2 (dac_fine). with the analog multiplexer, the signals s1 and s2 from the two buses can be combined to one pixel output at full pixel rate (40 mhz). however, the two analog signals s1 and s2 can also be available on two separate output pins to allow a higher pixel rate. the third dac (dac_dark) puts its value on the buses during the calibration of the output amplifi er. in case of nondestructive readout (no double sampling), bus1_r and bus2_r are continuously connected to the output of the dac_fine to provide a reference for the signals on bus1_s and bus2_s. the complete output amplifier ca n be put in standby by setting the corresponding bit in the amplifier register. figure 10. output amplifier architecture table 3. frame rate vs. resolution image resolution (y*x) frame rate [frames/s] frame readout time [ms] comment 3002 x 2210 5 187.5 full resolution 1501 x 1104 14 67 roi read out 640 x 480 89 11 11 + + bus1 s bus1_r bus2 s bus2_r dac_raw / dac_fine analog multiplexer programmable gain amplifiers pixel output pixel output 2 a2 a1 s2 s1 1 1 output drivers dac_dark stage 1 stage 2 stage 3 [+] feedback
ibis4-6600 cyii4sm6600ab document number: 001-02366 rev. *f page 10 of 34 stage 1: offset, fpn correction, and multiplexing in the first stage, the signals from the buses are subtracted and the offset from the dacs is added. after a system reset, the analog multiplexer is configured for two outputs (see the bit settings in the amplifier register on page 22). in case one_out is set to 1, the two signals s1 and s2 are multiplexed to one output (output 1). the amplifiers of stage 2 and stage 3 of the second output path are then put in standby. the speed and power consumption of the first stage can be controlled through the resistor connected to cmd_out_1. stage 2: programmable gain amplifier the second stage provides the gain, which is adjustable between 1.36 and 17.38 in steps of approximately 20.25 (~1.2). an overview of the gain settings is given in ta b l e 4 . the speed and power consumption of the second stage can be controlled through the resistor connected to cmd_out_2. stage 3: output drivers the speed and power consumption of the third stage can be controlled through the resistor connected to cmd_out_3. the output drivers are designed to drive a 20 pf output load at 40 msamples/s with a bias resistor of 100 k . offset dacs figure 11 shows how the dac registers influence the black reference voltages of the two different channels. the offset is mainly given through dac_raw. dac_fine can be used to shift the reference voltage of bus 2 up or down to compensate for different offsets in the two channels. figure 11. offset for the two ch annels through dac_raw and dac_fine table 4. pga gain settings bits dc gain bits dc gain 0000 1.36 1000 5.40 0001 1.64 1001 6.35 0010 1.95 1010 7.44 0011 2.35 1011 8.79 0100 2.82 1100 10.31 0101 3.32 1101 12.36 0110 3.93 1110 14.67 0111 4.63 1111 17.38 dac_raw d ac _ raw _ reg <0:7 out dac_fine vdda out 10k 200k 50k 50k 10k 200k blackref bus1 blackref bus2 gnda d ac _ fine _ reg <0:7 rcal rcal pad rcal _ dac _ out floating rcal v cal + note that in this figure, ?k? represents k . [+] feedback
ibis4-6600 cyii4sm6600ab document number: 001-02366 rev. *f page 11 of 34 assume that v outfull is the voltage that depends on the bit values that are applied to the dac and ranges from: externally, the output range of dac_raw can be changed by co nnecting a resistor rcal to rcal_dac_out and applying a voltage v cal . the output voltage v out of dac_raw follows the relation (r = 10 k ). special case: r cal = then v out = v outfull (for example, for dac_fine) rcal = 0, vcal = gnd .... ............ ............. then v out = v outfull /2 a similar relation holds for the output rang e of dac_dark (rcal_dac_dark can be used to tune the output range of this dac). analog to digital converter the ibis4-6600 has a two 10-bit flash analog digital converters. the adcs are electrically separa ted from the image sensor. the inputs of the adc must be tied externally to the outputs of th e output amplifiers. one adc samples the even columns and the oth er samples the odd columns. al ternatively, one adc can also sample all the pixels. setting the adc reference voltages figure 12. adc resistor ladder the internal resistance has a value of approximately 577 . only 277 of this internal resistance is actually used as reference for the internal adc. this causes the actual adc voltage range to become half of the voltage difference between vhigh_adc and vlow_adc. this results in the values listed ta b l e 6 for the external resistors. table 5. adc specifications parameter specification input range set by external resistors (refer the section setting the adc reference voltages ) quantization 10 bits nominal data rate 20 msamples/s dnl(linear conversion mode) typ. < 0.4 lsb rms inl (linear conversion mode) typ. < 3.5 lsb input capacitance < 2 pf conversion law linear/gamma corrected ) 11111111 ( ) 2 1 1 ( ) 00000000 ( 0 : 8 values bit vdda values bit v outfull o cal cal outfull cal cal out v r r r v r r r r v 2 2 150 ohm (esd) radc = 577 ohm internal gnd vlow_adc ~ 0.42v vhigh_adc ~ 1.5v 277 ohm vdda_adc high reference voltage used by adc 150 ohm (esd) low reference voltage used by adc table 6. adc resistor values resistor value ( ) rvhigh_adc 560 rinternal 577 rvlowadc 220 [+] feedback
ibis4-6600 cyii4sm6600ab document number: 001-02366 rev. *f page 12 of 34 sub sample modes to increase the frame rate for lower resolution and regions of interest, several sub samplin g modes are implemented. the possible sub sample modes are listed in ta b l e 7 . the bits can be programmed in the image_ core register (refer table 10 on page 17). to preserve the color information, two adjacent pixels are read in any mode. the number of pixels that is not read varies from mode to mode. this is designed as a repeated block 24 pixels wide, which is the lowest common multiple of the modes described. including the dummy pixels and the two additional rows/columns, the number of starting coordinates for the x and y shift register is 99 in the x direction and 138 in the y direction. the total number of pixels, excluding dummy pixels, is a multiple of 24, and two additional pixels to have the same window edges independently of the sub sampling mode. in the x direction, two columns are always addressed at the same moment, because the signals from the odd and even columns must be put simultaneously on the corresponding bus. in the y direction, the rows are addressed one by one. this results in slightly different implementations of the sub-sampling modes for the two directions (refer figure 13 and figure 14 on page 13). figure 13. x-sub sampling table 7. subsample patterns mode bits read step description a 000 2 2 default mode b 001 2 4 (skip 2) c 010 2 6 (skip 4) d 011 2 8 (skip 6) e 1xx 2 12 (skip 10) a b c d e shift register logic selecting 2 collumns shift register logic selecting 2 collumns shift register logic selecting 2 collumns shift register logic selecting 2 collumns shift register logic selecting 2 collumns shift register logic selecting 2 collumns shift register logic selecting 2 collumns shift register logic selecting 2 collumns shift register logic selecting 2 collumns shift register logic selecting 2 collumns shift register logic selecting 2 collumns shift register logic selecting 2 collumns 24 column amplifiers bus1_s bus1_r bus2_s bus2_r scan direction [+] feedback
ibis4-6600 cyii4sm6600ab document number: 001-02366 rev. *f page 13 of 34 figure 14. y-sub sampling figure 15 on page 14 shows the pixels read out in each color sub sampling mode. shift re g isters on pixel pitch lo g ic selectin g 1row a b c d e scan direction table 8. frame rate vs. sub sample mode mode ratio resolution (y*x) frame time [ms] frame time [ms] a 1:1 3002 x 2210 187.4 5.3 b 1:4 1502 x 1106 52.3 19.1 c 1:9 1002 x 738 25.7 38.9 d 1:16 752 x 554 15.8 63.2 63.2 1:36 502 x 370 8.2 121.2 vga (p) 640 x 480 12.3 81.5 vga (p) + 23 663 x 503 13.1 76.4 vga (l) 480 x 640 11.1 89.9 vga(l) + 23 503 x 663 11.9 83.7 [+] feedback
ibis4-6600 cyii4sm6600ab document number: 001-02366 rev. *f page 14 of 34 figure 15. pixel readout in various subsample modes 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 01234567891011121314151617181920212223 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 mode a mode b 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 mode c mode d 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 01234567891011121314151617181920212223 mode e [+] feedback
ibis4-6600 cyii4sm6600ab document number: 001-02366 rev. *f page 15 of 34 electronic shutter an electronic shutter similar to a rolling curtain is implemented on-chip. as shown in figure 17 , there are two y shift registers. one shift register points to the row that is currently being read ou t. the other shift register points to the row that is currently being reset. both pointers are shifted by the same y-clock and move over the focal plane. the integration time is set by the delay between b oth pointers. figure 16. electronic shutter in case of a mechanical shutter, the two sh ift registers can be combined to simultaneously apply the pulses from both sides of the pixel array. this is to halve the influence of the parasitic rc times of the reset and select li nes in the pixel array. this ca n result in a reduction of the row blanking time. this is the case when fast_reset in the sequencer register is set to 1, or in the nondestructive readout modes 1 and 2. figure 17. electronic rolling shutter operation integration time readout pointer reset pointer time axis line number reset sequence frame time integration time [+] feedback
ibis4-6600 cyii4sm6600ab document number: 001-02366 rev. *f page 16 of 34 high dynamic range modes double slope integration the ibis4-6600 has a feature ca lled double slope integration to increase the optical dynamic range of the sensor. the pixel response can be extended over a lar ger range of light intensities by using a "dual slope integration" (patents pending). this is obtained by adding charge packets from a long and a short integration time in the pixel during the same exposure time. figure 18 shows the response curve of a pixel in dual slope integration mode. the curve also shows the response of the same pixel in linear integration mode at the same light levels, with a long and short integration time. dual slope integration is obtained by feeding a lower supply voltage to vdd_reset_ds (for ex ample, apply 2.0v to 2.5v). note that for normal (single slope) operation, vdd_reset_ds must have the same value as vdd_reset. the difference between vdd_reset_ds and vd d_reset determines the range of the high sensitivity, and as a result the output signal level at which the transition between high and low sensitivity occurs. put the amplifier gain to the lowest value where the analog output swing covers digital input swing of the adc. increasing the amplification too much may boost the high sensitivity part over the whole adc range. the electronic shutter determines the ratio of integration times of the two slopes. the high sensitivity ramp corresponds to "no electronic shutter", thus maximal integration time (frame read out time). the low sensitivity ramp corresponds to the electronic shutter value that is obtained in normal operation. figure 18. double slope response nondestructive read out (ndr) the default mode of operation of the sensor is with fpn correctio n (double sampling). however, the sensor can also be read out in a nondestructive method. after a pixel is init ially reset, it can be read multiple time s, without being reset. the initial rese t level and all intermediate signals can be recorded. high light levels saturate the pixels quickly, but a useful signal is obtained from the e arly samples. for low light levels, use the later or latest samples. essentially an active pixel array is read multiple times, and r eset only once. the external system intel ligence interprets the data. table 9 on page 17 summarizes the advantages and disadvantages of nondestructive readout. figure 19. principle of nondestructive readout 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 0% 20% 40% 60% 80% 100% relative exposure (arbitrary scale) output signal [v] dual slope operation long integration time short integration time time [+] feedback
ibis4-6600 cyii4sm6600ab document number: 001-02366 rev. *f page 17 of 34 sequencer and registers figure 4 on page 6 showed several control signals that are needed to operate the sensor in a particular sub sampling mode, with a certain integration time, output amplifier gain, and more. most of these signals are gener ated on-chip by the sequencer that uses only a few control signals. these control signals must be generated by th e external system: sys_clock, which defines the pixel rate (nominal 40 mhz), y_start pulse, which indicates the start of a new frame, y_clock, which selects a new row and starts the row blanking sequence, including the synchronization and loading of the x-register. the relative position of the puls es is determined by a number of data bits that are uploaded in internal registers through a serial to parallel interface (spi). internal registers ta b l e 1 0 lists the internal registers with a short description. the registers are discussed in more detail in the following sections. table 9. ndr: advantages and disadvantages advantages disadvantages low noise, because it is true cds. in t he order of 10 e- or below. system memory required to record the reset level and the intermediate samples. high sensitivity, because the conv ersion capacitance is kept rather low. requires multiples readings of each pixel, thus higher data throughput. high dynamic range, because the results include signals for short and long integrations times. requires system level digital calculations. table 10. list of internal registers register bit name description 0 (0000) 11:0 sequencer register selection of mode, granularity of t he x sequencer clock, calibration, default value <11:0>:"000100000000" 0 ndr mode of readout: ndr = 0: normal readout (double sampling) ndr = 1: non-destructive readout 1:2 ndr_mode 4 different modes of nondestru ctive readout (no influence if ndr = 0) 3 reset_black 0 = normal operation 1 = reset of pixels before readout 4 fast_reset 0 = electronic shutter operation 1 = addressing from both sides 5frame_cal_mode0 = fast 1 = slow 6 line_cal_mode 0 = fast 1 = slow 7 cont_charge 0 = normal mode 1 = continuous precharge 8 gran_x_seq_lsb granularity of the x sequencer clock 9 gran_x_seq_msb 10 black 0 = normal mode 1 = disconnects column amplifiers from buses, output of amplifier equals dark reference level 11 reset_all 0 = normal mode 1 = continuous reset of all pixels 1 (0001) 10:0 nrof_pixels number of pi xels to count (x direction). max. 2222/2 (2210 real + 12 dummy pixels). default value <10:0>:"01000000000" [+] feedback
ibis4-6600 cyii4sm6600ab document number: 001-02366 rev. *f page 18 of 34 2 (0010) 11:0 nrof_lines number of lines to count (y direction) max. 3014 (3002 real + 12 dummy pixels) default value <11:0>:"101111000110" 3 (0011) 11:0 int_time integration time default value <11:0>:"000000000001" 4 (0100) 7:0 delay delay of sequencer pulses default value <7:0>:"00000011" 0:3 delay_pix_valid delay of pix_valid pulse 4:7 delay_eol/eof delay of eol/eof pulses 5 (0101) 6:0 x_reg x start position (0 to 98) default value <6:0>:"0000000" 6 (0110) 7:0 y_reg y start position (0 to 137) default value <7:0>:"00000000" 7 (0111) 7:0 image core register default value <7:0>:"00000000" 1:0 test_mode lsb: odd, msb: even 0 = normal operation 4:2 x_subsample sub sampling mode in x-direction 7:5 y_subsample sub sampling mode in x-direction 8 (1000) 9:0 amplifier register default value <9:0>:"0000010000" 3:0 gain<3:0> output amplifier gain setting 4 unity 0 = gain setting by gain<3:0> 1 = unity gain setting 5 one_out 0 = two analog outputs 1 = multiplexing to one output (out_1) 6 standby 0 = normal operation 1 = amplifier in standby mode 7:9 delay_clk_amp delay of pixel clock to output amplifier 9 (1001) 7:0 dac_raw_reg amplifier dac raw offset default value <7:0>:"10000000" 10 (1010) 7:0 dac_fine_reg amplifier dac fine offset default value <7:0>:"10000000" 11 (1011) 7:0 dac_dark_reg dac dark reference on output bus default value <7:0>:"10000000" table 10. list of internal registers (continued) register bit name description [+] feedback
ibis4-6600 cyii4sm6600ab document number: 001-02366 rev. *f page 19 of 34 register descriptions sequencer register a. ndr (bit 0) in normal operation (ndr = 0), the sensor operates in double sampling mode. at the start of each row readout, the signals from the pixels are sampled, the row is reset, and the signals from the pixels are sampled again. the values are subtracted in the output amplifier. when ndr is set to 1, the sensor operates in nondestructive readout (ndr) mode (refer ta b l e 11 ). b. ndr_mode (bit 1 and 2) these bits only influence the operation of the sensor in case ndr (bit 0) is set to 1. there are two modes for nondestructive readout (mode 1 and 2). each mode needs two different frame readouts (setting 1 and 2 for mode 1, setting 3 and 4 for mode 2). a reset/readout sequence (reset_seq) and then one or several pure readout sequences (called read_seq hereafter). ta b l e 11 gives an overview of the different ndr modes. mode 1 in this mode, the sensor is readout in the same method as for the nondestructive readout. however, electronic shutter control is not possible in this case, that is , the minimal (integration) time between two readings is equal to the number of lines that has to be read out (frame read time). the row lines are clocked simultaneously (left and right clock pulses are equal). mode 2 in this mode, it is possible to have a shorter integration time than the frame read time. rows are alternatingly read out with the left and right pointer. these two pointers can point to two different rows (see int_time register). the integration time between two readings of the same row is equal to the number of lines that is set in the int_time register multiplied by 2 plus 1, and is the minimal one line read time. in setting 3, the row that is read out by the left pointer is reset and read out (first y_clock), and the row that is read out by the right pointer is read out without being reset (second y_clock). in setting 4, both rows are r ead out without being reset (on the first y_clock the row is read out by the left pointer; on the second y_clock the row is read out by the right pointer). for both modes, the signals are read out through the same path as with destructive readout (dou ble sampling), but the buses that are carrying the reset signals in destructive rea dout, are set to the voltage given by dac_dark in nondestructive readout. 12 (1100) 10:0 adc register default value <10:0>:"00000000000" 0 standby_1 0 = normal operation 1 = adc in standby 1 standby_2 2 one 0 = multiplexing of two adc outputs 1 = disable multiplexing 3 switch if one = 0: delay of output with one (ext _clk = 0) or half (ext_clk = 1) clock cycle if one = 1: switch between two adcs 4 ext_clk 0 = internal clock (same as clock to x shift register and output amplifier) 1 = external clock 5 tristate 0 = normal operation 1 = outputs in tristate mode 6:8 delay_clk_adc delay of clock to adcs and digital multiplexer 9 gamma 0 = linear conversion 1 = 'gamma' law conversion 10 bitinvert 0 = no inversion of bits 1 = inversion of bits 13 (1101) reserved 14 (1110) reserved 15 (1111) reserved table 10. list of internal registers (continued) register bit name description table 11. overview of ndr modes. setting bits ndr mode sequence 1 00 1 reset 2011read 3 10 2 reset 4112read [+] feedback
ibis4-6600 cyii4sm6600ab document number: 001-02366 rev. *f page 20 of 34 c. reset_black (bit 3) if reset_black is set to 1, each line is reset before it is read out (except for the row that is read out by the right pointer in ndr mode 2). this may be useful to obtain black pixels. d. fast_reset (bit 4) the fast reset option (fast_reset = 1) might be useful in case a mechanical camera shutter is used. the fast reset is done on a row-by-row basis, not by a global reset. a global reset means charging all the pixels at the same time, which may result in a huge peak current. therefore, the rows can be scanned rapidly while the left and right shift registers are both controlled identically, so that the reset lines over the pixel array are driven from both sides. this reduces the reset (row blanking) time (when fast_reset = 1 the smal lest x-granularity can be used). after the row blanking time, the row is reset and y_clock can be a sserted to rese t the next row. after a certain integration time, the read out can be done in a similar method. the y shift registers are again synchronized to the first row. both shift registers are driven identically, and all rows and columns are scanned for (destructive) readout. fast_reset = 1 puts the sequencer in such mode that the left and right shift registers are both controlled identically. e. output amplifier calibration (bit 5 and 6) bits frame_cal_mode and line_cal_mode define the calibration mode of the output amplifier. during every row-blanking period, a calibration is done of the output amplifier. there are two calibration modes. the fast mode (= 0) can force a calibration in one cycle. however, it is not accurate and suffers from ktc noise, while the slow mode (= 1) can only make incremental adjustments and is noise free. approximately 200 or more "s low" calibrations have the same effect as one "fast" calibration. different calibration modes can be set at the beginning of the frame (frame_cal_mode bit) and for every subsequent row that is read (line_cal_mode bit). f. continuous charge (bit 7) for some applications, it might be necessary to use continuous charging of the pixel columns in stead of a precharge on every row sample operation. setting bit cont_charge to 1 activates this function. the resistor connected to pin cmd_col is used to control the current level on every pixel column. g. internal clock granularities the system clock is divided several times on-chip. the x-shift-register that contro ls the column/pixel readout, is clocked by half the system clock rate. odd and even pixel columns are switched to two separate buses. in the output amplifier, the pixel signals on the two buses can be combined to one pixel stream at 40 mhz. the clock that drives the x-seque ncer can be a multiple of 2, 4, 8, or 16 times the system clock. table 12 lists the settings for the granularity of the x-sequencer clock and the corresponding row blanking time (for ndr = 0). a row blanking time of 7.18 s is the baseline for almost all applications. h. black (bit 10) if black is set to 1, the internal black signal is held high contin- uously. as a result, the column amplifiers are disconnected from the buses, and the buses are set to the voltage given by dac_dark. the output of the am plifier equals the voltages from the offset dacs. i. reset_all (bit 11) if reset_all is set to 1, all the pixels are simultaneously put in a 'reset' state. in this state, t he pixels behave logarithmically with light intensity. if this stat e is combined with one of the ndr modes, the sensor can be used in a nonintegrating, logarithmic mode with high dynamic range. j. nrof_pixels register after the internal x_sync is generated (start of the pixel readout of a particular row), the pixel_valid signal goes high. the pixel_valid signal goes low when the pixel counter reaches the value loaded in the nrof_pixel register and an eol pulse is generated. due to the fact that two pixels are addressed at each internal clock cycle, the amount of pixels read out in one row is 2*(nrof_pixel + 1). k. nrof_lines register after the internal yl_sync is generated (start of the frame readout with y_start), the line counter increases with each y_clock pulse until it reaches the value loaded in the nrof_lines register and an eof pulse is generated. in ndr mode 2, the line counter increments only every two y_clock pulses and the eof pulse shows up only after the readout of the row indicated by the right shift register int_time register when the y_start pulse is applied (start of the frame readout), the sequencer generates the yl_sync pulse for the left y-shift register. this loads the left y-shift register with the pointer loaded in y_reg register. at each y_clock pulse, the pointer shifts to the next row and the integration time counter increases (increment only every two y_clock pulses in ndr mode 2) until it reaches the value loaded in the int_time register. at that moment, the yr_sync pulse for the right y-shift register is generated, which loads the right y-shift register with the pointer loaded in y_reg register (shown in figure 20 on page 21). table 12. granularity of x-sequencer clock and co rresponding row blanking time (for ndr = 0). gran_x_seq_msb/lsb x-sequencer clock row blanking time row blanking time [s] 00 2 x sys_clock 142 x tsys_clock 3.55 01 4 x sys_clock 282 x tsys_clock 7.05 10 8 x sys_clock 562 x tsys_clock 14.05 11 16 x sys_clock 1122 x tsys_clock 28.05 [+] feedback
ibis4-6600 cyii4sm6600ab document number: 001-02366 rev. *f page 21 of 34 figure 20. syncing of y-shift registers treg_int: difference between left and right pointer = integration counter until value "n" of int_time register is reached = int_time register in case of ndr = 0, the actual integration time tint is given by tintl: integration time [# lines] = nrof_lines register - int_time register + 1 in case of ndr = 1, ndr mode 1, the time tint between two readings of the same row is given by: tint:integration time [# lines] = nrof_l ines register + 1 in case of ndr = 1, ndr mode 2, the times tint1 and tint2 between two readings of the same row (alternatingly) are given by: tint1: integration time [# line s] = 2 * int_time register + 1 tint2: integration time [# lines] = 2 * (nrof_lines register + 1) - (2 * int_time register + 1) delay register the delay register can be used to delay the pixel_valid pulse (bits 0:3) and the eol/eof pulses (bits 4:7) to synchronize them to the real pixel values at the analog output or the adc output (which give additional delays depending on their settings). the bit settings and corresponding delay are indicated in ta b l e 1 3 . x_reg register the x_reg register determines t he start position of the window in the x-direction. in this direction, there are 2208 + 2 + 12 readable pixels. in the active pixel array, sub sampling blocks are 24 pixels wide and the columns are read two by two. therefore, the number of start positions equals 2208/24 +2/2 +12/2 = 92 + 1 + 6 = 99. y_reg register the y_reg register determines t he start position of the window in the y-direction. in this direction, there are 3000 + 2 + 12 readable pixels. in the active pixel array, sub sampling blocks are 24 pixels wide and the rows are read one by one. therefore, the number of start positions equals 3000/24 + 2/2 +12 = 125 + 1 + 12 = 138. image_core register bits 0:1 of the image_core register defines the several test modes of the image core. setting 00 is the default and normal operation mode. if the bit is set to 1, the odd (bit 0) or even (bit 1) columns are tight to v dd . these test modes can be used to tune the sampling point of the adcs to an optimal position. bits 2:7 of the image_core register define the sub sampling mode in the x-direction (bits 2:4) and in the y-direction (bits 5:7). the sub sampling modes and corresponding bit setting are given in the section analog to digital converter on page 11. sync of left shift-re g ister sync of right shift-re g ister line n t reg_int last line, followed by s y nc of left shift-re g ister t int syn c table 13. added delay by changing the delay register settings bits delay [# sys_clock periods] bits delay [# sys_clock periods] 0000 0 1000 6 0001 0 1001 7 0010 0 1010 8 0011 1 1011 9 0100 2 1100 10 0101 3 1101 11 0110 4 1110 12 0111 5 1111 13 [+] feedback
ibis4-6600 cyii4sm6600ab document number: 001-02366 rev. *f page 22 of 34 amplifier register a. gain (bits 0:3) the gain bits determine the gain setting of the output amplifier. they are effective only if unity = 0. the gains and corresponding bit setting are given in table 4 on page 10. b. unity (bit 4) if unity = 1, the gain setting of gain is bypassed and the gain amplifier is put in unity feedback. c. one_out if one_out = 0, the two output amplifiers are active. if one_out = 1, the signals from the two buses are multiplexed to output out1. the gain amplifier and output driver of the second path are put in standby. d. standby if standby = 1, the complete output amplifier is put in standby. this reduces the power consumption significantly. e. delay_clk_amp the clock that acts on the output amplifier can be delayed to compensate for any delay that is introduced in the path from shift register, column selection logic, column amplifier, and buses to the output amplifier. setting '000' is used as a baseline. dac_raw_reg and dac_fine_reg register these registers determine the black reference level at the output of the output amplifier. bit setting 11111111 for dac_raw_reg register gives the highest offset voltage; bit setting 00000000 for dac_raw_reg register gives the lo west offset voltage. ideally, if the two output paths have no offset mismatch, the dac_fine_reg register must be set to 10000000. deviation from this value can be used to compensate the internal mismatch (see the section offset dacs on page 10). dac_raw_dark register this register determines the vo ltage level that is put on the internal buses during calibration of the output stage. this voltage level is also continuously put on the reset buses in case of nondestructive readout (as a reset level for the double sampling fpn correction). adc register a. standby_1 and standby_2 if only one or none of the adcs is used, the other or both adcs can be put in standby by setting the bit to 1. this significantly reduces the power consumption. b. one if out1 and out2 are both used and connected to adc_in1 and adc_in2 respectively, one must be 0 to use both adcs and to multiplex their output to adc_d<9:0>. if one = 1, the multiplexing is disabled. c. switch if the two adcs are used (one = 0) and internal pixel clock (ext_clk = 0), the adc output is delayed with one system clock cycle if switch = 1. if the two adcs are used (one = 0) and an external adc clock (ext_clk = 1) is applied, the adc output is delayed with half adc clock cycle if switch = 1. if only one adc is used, the digital multiplexing is disabled by one = 1, but switch selects which adc output is on adc_d<9:0> (switch = 0: adc_1, switch = 1: adc_2). d. ext_clk if ext_clk = 0, the internal pixel clock (that drives the x-shift registers and output amplifier, that is, half the system clock) is used as input for the adc clock. if ext_clk = 1, an external clock must be applied to pin adc_clk_ext (pin 46). e. tristate if tristate = 1, the adc_d<9:0> outputs are in tri-state mode. f. delay_clk_adc the clock that finally acts on the adcs can be delayed to compensate for any delay introduc ed in the path from the analog outputs to the input stage of the adcs. the same settings apply for the delay that can be given to the clock acting on the output amplifier (see ta b l e 1 4 ). the best setting also depends on the delay of the output amplifier c lock and the load of the output amplifier. it must be used to optimize the sampling moment of the adcs with respect to the analog pixel input signals. setting '000' is used as a baseline. g. gamma if gamma is set to 0, the adc input to output conversion is linear, otherwise the conversion follows a 'gamma' law (more contrast in dark parts of the window, lower contrast in the bright parts). h. bitinvert if bitinvert = 0, 0000000000 is the conversion of the lowest possible input voltage, otherwise the bits are inverted. table 14. added delay by changing the delay_clk_amp bit settings bits delay [ns] bits delay [ns] 000 1.7 100 inversion + 8.3 001 2.9 2.9 inversion + 9.7 010 4.3 110 inversion + 11.1 011 6.1 111 inversion + 12.3 [+] feedback
ibis4-6600 cyii4sm6600ab document number: 001-02366 rev. *f page 23 of 34 serial to parallel interface to upload the sequencer registers, a dedicat ed serial to parallel interface (spi) is implemented. 16 bits (4 address bits + 12 data bits) must be uploaded serially. the address must be uploaded first (msb first), then the data (also msb first). the elementary unit cell is shown in figure 21 . sixteen of these cells ar e connected in series, having a common spi_clk form the entire uploadable parameter block. dout of one cell is connecte d to spi_data of the next cell (maximum speed is 20 mhz). the uploaded settings on the address/data bus are loaded into the correc t register of the sensor on the rising edge of signal reg_c lock and become effective immediately. figure 21. spi interface timing diagrams sequencer control signals there are 3 control signals that operate the image sensor: sys_clock y_clock y_start these control signals must be generated by the external system with the following time constraints to sys_clock (rising edge = active edge): tsetup >7.5 ns thold > 7.5 ns it is important that these signals are free of any glitches. figure 22. relative timing of the three control signals d q c d q c spi_data to address/data bus dout spi_clk reg_clock 16 outputs to address/data bus spi_clk spi_data unity cell e ntire uploadable addres s block reg_clock a 3 a 2 a 1d0 reg_clock spi_clk spi_data internal register upload [+] feedback
ibis4-6600 cyii4sm6600ab document number: 001-02366 rev. *f page 24 of 34 basic frame and line timing the basic frame and line timing of the ibis4-6600 sensor is shown in figure 23 . the pulse width of y_clock must be a minimum of one clock cycle and three clock cycles for y_start. as long as y_clock is applied, the sequencer stays in a suspended state. both eof and eol can be tied to y_start (eof) and y_clock (eol) if both signals are delayed with at least 2 sys_clock periods to let the sensor run automatically. figure 23. basic frame and line timing t1 row blanking time: during this period, the x-sequencer generate s the control signals to sample the pixel signal and pixel reset levels, and start the readout of one line. it depends on the granularity of the x-sequencer clock (see table 12 on page 20). t2 pixels counted by pixel counter until the value of nrof_pixel s register is reached. pixel_ valid goes high when the internal x_sync signal is generated. in other words, when the readout of the pixels is star ted. pixel_valid goes low when the pixel counter reaches the value loaded in the nrof_pixels register. eol goes high sys_clock cycle after the falling edge of pixel_val id. t3 eof goes high when the line counter reaches the value loaded in the nrof_lines register and the line is read (pixel_valid goes low). t4 the time delay between successive y_clock pulses needs to be equal to avoid any horizontal illumination (integration) discrepancies in the image. [+] feedback
ibis4-6600 cyii4sm6600ab document number: 001-02366 rev. *f page 25 of 34 pixel output timing using two analog outputs figure 24. pixel output timing using two analog outputs the pixel signal at the out1 (out 2) output becomes valid after four sys_clock cycles when the internal x_sync (equal to start of pixel_valid output) appears (see figure 24 ). the pixel_valid and eol/eof pulses can be delayed by the user through the delay register. t1: row blanking time (see table 12 on page 20) t2: 4 sys_clock cycles. multiplexing to one analog output the pixel signal at the out1 output becomes valid after five sys_clock cycles when the internal x_sync (equal to start of pixel_valid output) appears (see figure 25 ). the pixel_valid and eol/eof pulses can be delayed by the user through the delay register. t1: row blanking time t2: 5 sys_clock cycles. figure 25. pixel output timing multiplexing to one analog output [+] feedback
ibis4-6600 cyii4sm6600ab document number: 001-02366 rev. *f page 26 of 34 adc timing two analog outputs figure 26 shows the timing of the adc using two analog outputs. inter nally, the adcs sample on the falling edge of the adc_clock (in case of internal clock, the clock is half the sys_clock). t1: each adc has a pipeline delay of 2 adc_clock cycles. this results in a total pipeline delay of four pixels. figure 26. adc timing us ing two analog outputs one analog output figure 27 shows the timing of the adc using o ne analog output. internally, the adc samp les on the falling edge of the adc_clock. t1: the adc has a pipeline delay of 2 adc_clock cycles. figure 27. adc timing using one an alog output [+] feedback
ibis4-6600 cyii4sm6600ab document number: 001-02366 rev. *f page 27 of 34 pin information the following table lists all the pins and their functions. ther e are a total of 68 pins. all pins with the same name can be co nnected together. table 15. pin list pin pin name pin type expected voltage [v] pin description 1 cmd_col_ctu input 0 biasing of columns (ctu). decouple with 100 nf to gnda. 2 cmd_col input 1.08 biasing of columns. connect to v dda with r = 10 k and decouple to gnda with c = 100 nf. 3 cmd_colamp input 0.66 biasing of column amplifiers. connect to v dda with r = 100 k and decouple to gnda with c = 100 nf. 4 cmd_colamp_ctu input 0.37 biasing of column amplifiers. connect to v dda with r = 10 m and decouple to gnda with c = 100 nf. 5 rcal_dac_dark input 1.27 at code 128 dac_dark reg biasing of dac for dark referenc e. can be used to set output range of dac. default: decouple to gnda with c = 100 nf 6 rcal_dac_out input 0 biasing of dac for output dark level. can be used to set output range of dac. default: connect to gnda 7v dda power 2.5 v dd of analog part [2.5v] 8 gnda power 0 gnd (&substrate) of analog part 9v ddd power 2.5 v dd of digital part [2.5v] 10 gndd power 0 gnd (&substrate) of digital part 11 cmd_out_1 input 0.78 biasing of first stag e output amplifiers. connect to vddamp with r = 50 k and decouple to gndamp with c = 100 nf. 12 cmd_out_2 input 0.97 biasing of second stage output amplifiers. connect to vddamp with r = 25 k and decouple to gndamp with c = 100 nf. 13 cmd_out_3 input 0.67 biasing of third stage output amplifiers. connect to vddamp with r = 100 k and decouple to gndamp with c = 100 nf. 14 spi_clk input - clock of digital parameter upload. shifts on rising edge. 15 spi_data input - serial address and data input. 16-bit word. address first. msb first. 16 vddamp power 2.5 v dd of analog output [2.5v] (can be connected to v dda ) 17 cmd_fs_adc input 0.73 biasing of first stage adc. connect to vdda_adc with r = 50 k and decouple to gnda_adc with c = 100 nf. 18 cmd_ss_adc input 0.73 biasing of second stage adc. connect to vdda_adc with r = 50 k and decouple to gnda_adc. 19 cmd_amp_adc input 0.59 biasing of input stage adc. connect to vdda_adc with r = 180 k and decouple to gnda_adc with c = 100 nf. 20 gndamp ground 0 gnd (&subs trate) of analog output 21 out1 output black level: 1 at code 190 dac_raw register analog output 1 22 adc_in1 input see out1. analog input adc 1 23 vddamp power 2.5 v dd of analog output [2.5v] (can be connected to v dda ) 24 out2 output black level: 1 at code 190 dac_raw register analog output 2 25 adc_in2 input see out2. analog input adc 2 26 v ddd power 2.5 v dd of digital part [2.5v] 27 gndd power 0 gnd (&substrate) of digital part 28 gnda power 0 gnd (&substrate) of analog part [+] feedback
ibis4-6600 cyii4sm6600ab document number: 001-02366 rev. *f page 28 of 34 29 v dda power 2.5 v dd of analog part [2.5v] 30 reg_clock input - register clock. data on internal bus is copied to corresponding registers on rising edge. 31 sys_clock input - system clock defining t he pixel rate (nominal 40 mhz, 50% 5% duty cycle) 32 sys_reset input - global syst em reset (active high) 33 y_clk input - line clock 34 y_start input - start frame readout 35 gndd_adc power 0 gnd (&substrate) of digital part adc 36 vddd_adc power 2.5 v dd of digital part [2.5v] adc 37 gnda_adc power 0 gnd (&subs trate) of analog part 38 vdda_adc power 2.5 v dd of analog part [2.5v] 39 vhigh_adc input 1.5 adc high reference voltage (for example, connect to vdda_adc with r = 560 and decouple to gnda_adc with c = 100 nf) 40 vlow_adc input 0.42 adc low reference voltage (for example, connect to gnda_adc with r = 220 and decouple to gnda_adc with c = 100 nf) 41 gnda_adc power 0 gnd (&subs trate) of analog part 42 vdda_adc power 2.5 v dd of analog part [2.5v] 43 gndd_adc power 0 gnd (&substrate) of digital part adc 44 vddd_adc power 2.5 v dd of digital part [2.5v] adc 45 vdd_reset_ds power 2.5 (for no dual slope) variable reset voltage (dual slope) 46 adc_clk_ext input - external adc clock 47 eol output - diagnostic end of line signal (produced by sequencer), can be used as y_clk 48 eof output - diagnostic end of frame signal (produced by sequencer), can be used as y_start 49 pix_valid output - diagnostic signal. high during pixel readout 50 temp output - temperature measurement. output voltage varies linearly with temperature. 51 adc_d<9> output - adc data output (msb) 52 vdd_pix power 2.5 v dd of pixel core [2.5v] 53 gnd_ab power 0 anti-blooming ground. se t to 1v for improved anti-blooming behavior 54 adc_d<8> output - adc data output 55 adc_d<7> output - adc data output 56 adc_d<6> output - adc data output 57 adc_d<5> output - adc data output 58 adc_d<4> output - adc data output 59 adc_d<3> output - adc data output 60 vdd_reset power 2.5 reset voltage [2.5v]. highest voltage to the chip. 3.3v for extended dynamic range or 'hard reset'. 61 adc_d<2> output - adc data output 62 adc_d<1> output - adc data output 63 adc_d<0> output - adc data output (lsb) table 15. pin list (continued) pin pin name pin type expected voltage [v] pin description [+] feedback
ibis4-6600 cyii4sm6600ab document number: 001-02366 rev. *f page 29 of 34 note on power on behavior at power on, the chip is in an undefined stat e. it is advised that the power on is accompanied by the assertion of the sys_cloc k and a sys_reset pulse that puts a ll internal registers in their default state (a ll bits are set to 0). the x-shift registers ar e in a defined state after the first x_sync, which occurs a few microseconds after the first y_star t and y_clock pulse. before this x_sync, the chip may draw more current from the analog power supply v dda . it is therefore favorable to have separate analog and digital supplies. the current spike (if there are any) may also be avoi ded by a slower ramp up of the analog power supply or by disconn ecting the resistor on pin 3 (cmd_colamp) at startup. 64 bs_reset input - boundary scan (allows debugging of internal nodes): reset. tie to gnd if not used. 65 bs_clock input - boundary scan (allows debugging of internal nodes): clock. tie to gnd if not used. 66 bs_din input - boundary scan (allows debugging of internal nodes): in. tie to gnd if not used. 67 bs_bus output - boundary scan (allows debugging of internal nodes): bus. leave floating if not used. 68 cmd_dec input 0.74 biasing of x and y decoder. connect to v ddd with r = 50 k and decouple to gndd with c = 100 nf. table 15. pin list (continued) pin pin name pin type expected voltage [v] pin description [+] feedback
ibis4-6600 cyii4sm6600ab document number: 001-02366 rev. *f page 30 of 34 package information figure 28. 68 pin lcc packaging outline (001-05458) glass 68 1 61 60 9 10 26 27 43 44 61 1 9 68 10 60 26 44 27 43 part no. table 001-05458 ** [+] feedback
ibis4-6600 cyii4sm6600ab document number: 001-02366 rev. *f page 31 of 34 figure 29. 84 pin jlcc packaging outline (001-05462) glass 84 jlcc packaging ou 001-054 84 1 11 12 32 33 53 54 74 75 53 33 54 32 74 12 11 1 84 75 a view a 001-05462 ** [+] feedback
ibis4-6600 cyii4sm6600ab document number: 001-02366 rev. *f page 32 of 34 glass lid specifications monochrome sensor a d263 glass is used as protection glass lid on top of the ibis 4-6600 monochrome sensors. the refraction index of the d263 glas s lid is 1.52. figure 30 shows the transmission characteristics of the d263 glass. figure 30. transmittance curve of the d263 cover glass lid storage and handling storage conditions handling and soldering conditions special care must be taken when soldering image sensors with color filter arrays (rgb color filters), onto a circuit board, because color filters are sensitive to high temperatures. prolonged heating at elevated temperatures may result in deterioration of the performanc e of the sensor. the following recommendations ensure that sensor performance is not compromised during end-use rs assembly processes. board assembly device placement onto boards must be done in accordance with strict esd controls for class 0, jesd22 human body model, and class a, jesd22 machine mode l devices. assembly operators must always wear all designated and approved grounding equipment. grounded wrist straps at esd protected workstations are recommended, including the use of ionized blowers. all tools must be esd protected. manual soldering when a soldering iron is used, the following conditions must be observed: use a soldering iron with temper ature control at the tip. the soldering iron tip temperature must not exceed 350c. the soldering period for each pin must be less than 5 seconds. reflow soldering figure 31 on page 33 shows the maximum recommended thermal profile for a reflow soldering system. if the temperature/time profile ex ceeds these recommendations, damage to the image sensor may occur. see figure 31 on page 33 for more details. precautions and cleaning avoid spilling solder flux on the cover glass, because bare glass and particularly glass with antir eflection filters may be adversely affected by the flux. avoid mechanical or particulate damage to the cover glass. it is recommended that isopropyl alcohol (ipa) be used as a solvent for cleaning the image se nsor glass lid. when using other solvents, it must be confirm ed beforehand whether the solvent can dissolve the package and/or the glass lid. 0 10 20 30 40 50 60 70 80 90 100 400 500 600 700 800 900 wavelength [nm] transmission [%] table 16. storage conditions description minimum maximum maximum temperature ?30 +85 c [+] feedback
ibis4-6600 cyii4sm6600ab document number: 001-02366 rev. *f page 33 of 34 figure 31. reflow soldering temperature profile rohs (pb-free) compliance this section reports the use of hazardous chemical substances as required by the rohs directive (excluding packing material). pb-free soldering ibis4-a-6600-m2 (serial numbers beyond 3694): this product is successfully tested for pb-free soldering processes, using a reflow temperature profile with maximum 260c, minimum 40s at 255c, and minimum 90s at 217c. ibis4-a-6600-c2: this product does not withstand a lead-free soldering process. maximum allowed reflow or wave soldering temperature is 220c. hand soldering is recommended for this part type. note that "intentional conten t" is defined as any material demanding special attention is contained into the inquired product by following cases: 1. a case that the previously me ntioned material is added as a chemical composition into the inquired product intentionally, to produce and maintain the required performance and function of the intended product. 2. a case that the previously m entioned material, which is used intentionally in the manufacturi ng process, is contained in or adhered to the inquired product. the following case is not treat ed as "intentional content": a case that the previously mentioned material is contained as an impurity into raw materials or parts of the intended product. the impurity is defined as a subst ance that cannot be removed industrially, or is produced at a process, such as chemical composing or reaction and cannot be removed technically. table 17. the chemical substances and information about any intentional content chemical substance intentional content portion containing intentional content lead no - cadmium no - mercury no - hexavalent chromium no - pbb (polybrominated biphenyls) no - pbde (polybrominated diphenyl ethers) no - [+] feedback
document number: 001-02366 rev. *f revised september 18, 2009 page 34 of 34 all products and company names mentioned in this document may be the trademarks of their respective holders. ibis4-6600 cyii4sm6600ab ? cypress semiconductor corporation, 2005-2009. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and international treaty provisions . cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. document history page sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution cente rs, manufacturer?s representatives, and distributors. for more infor- mation on image sensor products, please contact imagesensors@cypress.com . cypress offers standard and customized cmos image sensors for co nsumer as well as industrial and professional applications. consumer applications include the fast growing high volume cell phone, digital still cameras as well as automotive applications . cypress' cmos image sensors are characterized by very high pi xel counts, large area, very high frame rates, large dynamic range , and high sensitivity. document title: ibis4-6600 cyii4sm6600ab 6.6 mp cmos image sensor document number: 001-02366 rev. ecn submission date orig. of change description of change ** 384900 see ecn fwu origination. *a 402976 see ecn fwu preliminary notice removed. electro optical spec updated to characterization data. *b 418669 see ecn fvk table 15. adc resistor values changed. adc section added. figure 33 p41 corrected *c 502551 see ecn qgs converted to frame file *d 642596 see ecn fpw ordering information update *e 2649816 03/17/2009 pci/aesa final data sheet. changed ti tle from ?ibis4-a-6600 cmos image sensor? to ?ibis4-6600 cyii4sm6600ab 6.6 mp cmos image sensor?. updated typical response curve of the rgb filters on page 7 and added relative response graph on page 8. updated package diagrams and data sheet template. *f 2766198 09/19/09 nvea updated ordering information table [+] feedback

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